1. Technical Field
The present invention relates to a method of manufacturing a wafer level package.
2. Description of the Related Art
The trends in the electronics industry are to manufacture lighter and smaller products that provide faster speed, greater functionality, higher performance, and higher reliability at lower costs. An important technology that makes this possible is package technology, where the wafer level package (WLP) technology is receiving attention as an area of technology that enables the realizing of products with smaller sizes, lighter weights, and higher performances, etc.
FIG. 1 through FIG. 13 represent a flow diagram illustrating a method of manufacturing a wafer level package according to the related art. Looking at the method of manufacturing a wafer level package according to the related art with reference to FIG. 1 through FIG. 13, first, as illustrated in FIG. 1, over a semiconductor chip 102, on which a passivation layer 108 is formed such that an electrode pad 104 uncovered, a first insulation layer 106 may be stacked such that the electrode pad 104 is uncovered. Next, as illustrated in FIG. 2, a first seed layer 110 may be formed over the electrode pad 104 and the first insulation layer 106, to electrically connect the electrode pad 104 and the first seed layer 110. Next, as illustrated in FIG. 3, a plating resist 112 may be formed, in order to form a rewiring pattern 114 that electrically connects with the electrode pad 104. Next, as illustrated in FIG. 4, electroplating may be performed, using the first seed layer 110 as an electrode, to form the rewiring pattern 114. Next, as illustrated in FIG. 5, the plating resist 112 may be removed, and using the rewiring pattern 114 as a mask, portions of the first seed layer 110 open to the exterior may be etched. Next, as illustrated in FIG. 6, a second insulation layer 116 may be stacked, which leaves a portion of the rewiring pattern 114 uncovered. Next, as illustrated in FIG. 7, a second seed layer 118 may be formed over the uncovered portion of the rewiring pattern 114 and the second insulation layer 116. Next, as illustrated in FIG. 8, a plating resist 119 may be formed, which has an opening corresponding with the open portion of the rewiring pattern 114. Next, as illustrated in FIG. 9, electroplating may be performed, using the second seed layer 118 as an electrode, to form a metal pillar 120. Next, as illustrated in FIGS. 10 and 11, the plating resist 119 and the second seed layer 118 may be removed, and the surface of the semiconductor chip 102 may be molded with epoxy 122. Next, as illustrated in FIG. 12, portions of the molded epoxy 122 may be removed, such that a portion of the metal pillar 120 is uncovered. Next, as illustrated in FIGS. 12 and 13, a solder ball 124 may be attached to the metal pillar 120, and the solder ball 124 may be reflowed.
In the method of manufacturing a wafer level package according to the related art, the seed layer for plating the rewiring pattern and the seed layer for plating the metal pillar may be formed individually, and after the plating processes, etching processes may be required for removing the seed layers. Consequently, the manufacturing process can be complicated, and there is a higher risk of defects occurring during manufacture.
Also, the twofold stacking of insulation layers over the semiconductor chip, as well as the attaching of a solder ball, may cause increases in manufacturing costs.